1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel, and more particularly to an active device array substrate of an LCD panel.
2. Description of Related Art
With rapid development of image display technologies, cathode ray tube (CRT) displays that used to be applied in televisions or computers have been gradually replaced by LCDs. An LCD panel of the LCD is usually constituted by an active device array substrate, an opposite substrate, and a liquid crystal layer disposed between said two substrates. Besides, said two substrates are usually adhered to each other by sealant, so as to prevent liquid crystals from overflowing.
In general, the active device array substrate has an active area and a peripheral circuit area. In the active area, a plurality of pixels are disposed to form a pixel array. Besides, a peripheral circuit is formed in the peripheral circuit area. Each of the pixels includes a thin film transistor (TFT) and a pixel electrode connected thereto. Additionally, each of the pixels are surrounded by and electrically connected to two adjacent scan lines and two adjacent data lines. These scan lines and data lines are extended from the active area to the peripheral area and connected to the aforesaid peripheral circuit, and the peripheral circuit is then connected to external driver integrated circuits (ICs).
Due to demands on high image resolution and compactness of the LCD, the technology of mounting and packaging driver ICs on the LCD panel has evolved gradually from chip on board (COB) to tape automated bonding (TAB), and afterwards to chip on glass (COG) and chip on film (COF) of which fine pitches exist among pins. Here, the COF technique and the COG technique belong to a high-pin-count package technique by which the numbers of driver ICs and circuit boards for coupling can be reduced. As a result, the COF technique and the COG technique have little by little proceeded.
As the number of pins increases, line width and the pitch of the peripheral circuit correspondingly decrease, and thereby it is much more difficult to fabricate marks used for marking positions of the peripheral circuit or pin numbers thereof. In other words, the marks cannot be manufactured between traces by applying a conventional manufacturing process. Taking the current 4.0 micron process for example, the minimum width of the mark is approximately 12.0 microns, whereas the pitch between two traces in the current peripheral circuit is designed to be 22.0 microns in most cases. Besides, the minimum pitch is 9.0 microns. Hence, when the mark is planned to be formed between two traces, a distance from the mark to the two traces is required to be at least 9.0 microns, respectively, and thus the width of the mark must be less than 4.0 microns.
As such, in fabrication of the LCD panel at present, it is rather imperative to propose a way to overcome said defect and to prevent the same from occurring.